发明名称 PHASE-LOCKED LOOP CIRCUIT AND RECEPTION SYSTEM
摘要 PROBLEM TO BE SOLVED: To improve estimation characteristics of a signal estimator by rotating the phase of a receive signal according to the phase of the output signal of a voltage-controlled oscillator, detecting the impulse response of a transmission line, specifying a region used for series estimation and a region for replica generation, and performing series estimation by using a region specified by a region specifier for series estimation. SOLUTION: An impulse response detector 2 detects an impulse response in a preamble period shown in a form format. The optimum region for series estimation and replica generation in the detected impulse response are obtained by the region specifier 3 for series estimation and a region specifier 4 for replica generation. The regions of the impulse response used for series estimation and replica generation by which results having different impulse response waveforms are obtained are set. The impulse response of the region for series estimation is outputted to a delay decision freedback series estimator 5, and the impulse response for replica generation is outputted to a replica generator 6.
申请公布号 JP2000269948(A) 申请公布日期 2000.09.29
申请号 JP19990070406 申请日期 1999.03.16
申请人 NEC CORP 发明人 MARUYAMA SHUSUKE
分类号 H04B3/06;H04B1/10;H04B7/005;H04B15/06;H04L7/033;H04L25/02;H04L27/00 主分类号 H04B3/06
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