| 摘要 |
<p>PROBLEM TO BE SOLVED: To make performable a test of a semiconductor integrated circuit by use of a slow LSI tester and accordingly, to reduce the price of a product by using a test clock with which the input cycle start edge of a multiplied clock is synchronized with the edge of an external clock. SOLUTION: When a test mode setting signal TMD is set at an H level, an AND circuit 22 functions as a buffer circuit to a test clock T CLK. At the same time, the output of an inverter 23 is set at an L level and the output of an AND circuit 24 is fixed at an H level. Thereby, the clock T CLK is selected as an external bus operating clock B CLK. Meanwhile, when the signal TMD is set at an L level, the output of the circuit 22 is fixed at an H level and the output of the inverter 23 is set at an H level. Then the circuit 24 functions as a buffer circuit to a 4-multiplied clock N CLK. Thereby the clock N CLK is selected as the clock B CLK.</p> |
