| 摘要 |
<p>Disclosed is an apparatus for verifying a VLSI design at an early stage as well as a later stage, and particularly a VLSI emulator based on processors and reconfigurable chips. The model of the VLSI chip is divided into a functional part and an external interface part. The functional part is executed by a processing module having at least one processor, and the external interface part is executed by an external interface signal processor to generate real pin signals. The external interface part is implemented using reconfigurable circuits by programming the circuits. The communicating between the functional part and the external interface part is accomplished by transmitting and/or receiving control packets composed of control commands and/or or data. The intenal functional part and the external interface part are verified on a target system at an early stage of the VLSI design, which may reduce time for designing the VLSI and verifying and designing whole system.</p> |
