发明名称 SYSTEM AND METHOD FOR PERFORMING ASSERTION-BASED ANALYSIS OF CIRCUIT DESIGNS
摘要 Techniques for analyzing circuit design based on assertions (112). An assertion is associated with a circuit structure from the circuit design (114). The assertion (112) specifies a context of the circuit design (114) in which the circuit structure (110) is to be analyzed (110), an attribute associated with the circuit structure (110), and a constraint associated with the attribute. The present invention analyzes the circuit design (114) based on assertions and checks to identify one or more instances of the circuit structure (110) in the circuit design (114) which do not satisfy the constraint specified in the assertion. An assertion may also indicate an action to be performed if the circuit structure (114) does not satisfy the constraint specified in the assertion (112).
申请公布号 WO0057317(A1) 申请公布日期 2000.09.28
申请号 WO2000US06996 申请日期 2000.03.17
申请人 MOSCAPE, INC.;CHANDRA, RAJIT;MITRA, JOYDEEP;PARKS, STEVEN, B.;SOMANATHAN, CHANDRASEKHARA 发明人 CHANDRA, RAJIT;MITRA, JOYDEEP;PARKS, STEVEN, B.;SOMANATHAN, CHANDRASEKHARA
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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