发明名称 Verfahren und Tester zur Beaufschlagung eines elektronischen Bausteins mit einem Triggerimpuls
摘要 A unit (108) to be triggered, for example a memory, receives data under the control of Boundary Scan Test (BST) logic, via a BST chain (110). The invention utilizes a pulse circuit (202) which generates a pulse trigger for the unit (108) on the basis of a stimulus presented via the BST chain (110). This saves time, because it is no longer necessary to supply the entire pulse trigger via the BST chain and the supply of the stimulus now suffices.
申请公布号 DE69606129(T2) 申请公布日期 2000.09.28
申请号 DE1996606129T 申请日期 1996.10.09
申请人 JTAG TECHNOLOGIES B.V., EINDHOVEN 发明人 DE WIT, HENDRIKUS;STORK, CORNELIS F.J.M.
分类号 G01R31/3185;G11C29/32;(IPC1-7):G01R31/318;G06F11/267;G11C29/00 主分类号 G01R31/3185
代理机构 代理人
主权项
地址