| 摘要 |
<p>When a clock reproduction circuit (6) is locked, a phase comparator (9) detects a level difference DELTA E between a zero crossing point and a true 0 level. The level difference DELTA E represents an offset level and is output as an offset detection signal. After being planarized in the LPF (12), the level difference DELTA E is input to adders (14) and (15) so as to cancel a DC offset. <IMAGE></p> |
