发明名称 PLL circuit
摘要 <p>An oscillating signal of a VCO (7), after being divided by a divider (2), is input by a phase comparator (3). The phase difference between the divider (2) and a reference signal is detected by the phase comparator (3), and phase error is smoothed by a loop filter (4) to yield a phase error signal. The oscillating signal of the VCO 7 is also input by a frequency detector (9) and is detected to determine whether it is equal to a predetermined value or in a predetermined range. On the basis of this detection result, a frequency error signal is output. The frequency error signal and the phase error signal, after being added together, are input by the VCO (7) as a control signal so that the oscillation frequency is controlled. &lt;IMAGE&gt;</p>
申请公布号 EP1039640(A1) 申请公布日期 2000.09.27
申请号 EP20000302463 申请日期 2000.03.27
申请人 SANYO ELECTRIC CO., LTD. 发明人 YOSHIE, KAZUAKI
分类号 H03L7/095;H03L7/087;H03L7/089;H03L7/093;H03L7/107;H03L7/113;(IPC1-7):H03L7/087 主分类号 H03L7/095
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