Deposition process for gap filling high-aspect ratio features in integrated circuits

摘要

A technique for fabricating an integrated circuit in which a protective layer 303 of undoped silicon glass (USG) is deposited over conductive elements 302. A layer of low-k dielectric material 304 such as fluorosilicate glass (FSG) is deposited over the protective layer 303, preferably by high density plasma chemical vapour deposition (HDP-CVD). The process results in significantly improved gap fill capabilities for high aspect ratio conductive features (aspect ratio of order of two or more) with spacing between the features of less than 300nm. By virtue of the fluorine incorporation in the exemplary embodiment, a reduction of the order of 10% in line-to-line capacitance, CL-L, may be realised when compared to conventional undoped dielectric materials.