发明名称 |
Semiconductor device and method of fabricating same |
摘要 |
An N-type buried diffusion layer as a portion of the collector region of a bipolar transistor and an N-type buried diffusion layer of a memory cell region are simultaneously formed, and the buried diffusion layer of the memory cell region serves as a potential groove for electrons. The threshold voltage of a MOS transistor in the memory cell region is higher than the threshold voltage of a MOS transistor in a peripheral circuit region, preventing an increase in the standby current in the memory cell region. This increases the soft error resistance of the memory cell and prevents a decrease in the operating speed and an increase in the consumption power.
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申请公布号 |
US6124617(A) |
申请公布日期 |
2000.09.26 |
申请号 |
US19970964907 |
申请日期 |
1997.11.05 |
申请人 |
SONY CORPORATION |
发明人 |
YOSHIHARA, IKUO;KUROOKA, KAZUAKI |
分类号 |
H01L21/8222;H01L21/8234;H01L21/8244;H01L21/8248;H01L21/8249;H01L27/06;H01L27/10;H01L27/11;(IPC1-7):H01L31/119 |
主分类号 |
H01L21/8222 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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