| 摘要 |
Improved pipelined successive approximation analog-to-digital converter circuits are provided. Some embodiments of the present invention comprises two stages in which a first portion of the total bits are evaluated in the first stage of the circuit and then the residue is passed to the second stage of the circuit that evaluates the remaining portion. By operating both stages simultaneously, the throughput is increased. These embodiments utilize two matched buffers to isolate the first and second stages from switching errors of a sampling circuit and the loading effects of comparators associated with the two stages. In another embodiment, upon completion of the conversion of the MSBs, the remaining input signal or residue signal is amplified by a preamp and the output is subsequently sampled by a residue sample and hold circuit (S/H). After the residue is sampled by the residue S/H, the second stage begins to solve the least significant bits (LSBs). The second stage is a matched copy of the first stage. Furthermore, if the CDACs and the preamps corresponding to the two stages are matched, the actual value of the preamp gain does not affect converter linearity. In yet another embodiment, a single preamp buffer is switched between the first and second stages. The preamp provides buffering of the top plates of the capacitor array from the residue sampling switch.
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