Method and apparatus for a N-nary logic circuit using capacitance isolation

摘要

The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal. And finally, the logic device of the present invention includes a second transistor that couples the second internal evaluate node to the first intermediate node that is gated by the second wire of the first input signal. At most, one of the first internal evaluate node and the second internal evaluate node couples to the first intermediate node with the second transistor substantially preventing residual charge on the second internal evaluate node from being passed to the first intermediate node when the first input value corresponds to the first possible value.