发明名称 |
Phase locked loop and multi-stage phase comparator |
摘要 |
The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.
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申请公布号 |
US6125158(A) |
申请公布日期 |
2000.09.26 |
申请号 |
US19970996771 |
申请日期 |
1997.12.23 |
申请人 |
NORTEL NETWORKS CORPORATION |
发明人 |
CARSON, DAVE;DUNNE, ALAN;VEA, MATTHEW;GUEST, SCOTT;WYATT, ROBERT |
分类号 |
H03D13/00;H03L7/087;H03L7/091;H04L7/033;(IPC1-7):H03D3/24;H04L7/00;H04L25/00;H04L25/40 |
主分类号 |
H03D13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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