发明名称 A system for performing input and output operations to and from a processor
摘要 A system for performing input and output operations to and from a processor in which interrupts for I/O operations are conditionally generated internally rather than externally by (Super State TM ) microcode residing in a separate address space in memory in an area protected from the user. A (superblock) register in the processor points to the Super State area in memory. If the Super State mode is turned on, an interrupt is generated within the processor whenever the control table allows. The interrupt directs the processor to the register and hence to the Super State code. By way of example, the Super State code controls power and access to the port, decides whether to put the interrupt in memory and emulate the I/O, and counts access to the port. The invention provides a processor with the flexibility of performing I/O operations to and from memory and/or to a peripheral or to trap an interrupt into a new operating environment for device emulation. Device emulation and monitoring is allowed without considerable program overhead. The invention provides a powerful, efficient I/O control system which can change or adapt in response the changing demands of an application program.
申请公布号 US6125412(A) 申请公布日期 2000.09.26
申请号 US19930046109 申请日期 1993.04.09
申请人 CHIPS & TECHNOLOGIES, LLC 发明人 PICARD, JAMES A.;JONES, JR., MORRIS E.
分类号 G06F13/10;G06F13/12;G06F13/24;(IPC1-7):G06F13/00 主分类号 G06F13/10
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