| 摘要 |
PURPOSE: A pulse generating circuit is provided to generate a stable pulse by generating a transient pulse more delayed for a predetermined time than the transition timing of an output level. CONSTITUTION: A first pulse generating unit(1) inputs a clock signal and generates a pulse synchronized with the clock signal. A first PMOS transistor(2) is connected to a high potential power source through the source thereof, connected to an output side of the first pulse generating unit(1) through the gate thereof, and connected to an output line through a drain thereof. A first delay unit(4) is connected to the output line in an input side thereof and more delayed for a predetermined time than the transition timing of an output level to generate a transient pulse.
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