发明名称 MULTIPROCESSOR CONTROL SYSTEM
摘要 PROBLEM TO BE SOLVED: To decrease useless transactions by issuing a transaction from a present cluster when the data of the required transaction are prepared in the external cache of the other cluster. SOLUTION: When the external cache requests re-inputting concerning a transaction issued to a system bus 300, an SRAM buffer 112 correspondently stores the ID of that transaction and an address. An ID comparator 111 compares a transaction ID signal 110 reported from the external cache with the transaction ID in the SRAM buffer 112. Then, a selecting means 113 selects an address corresponding to the coincident transaction ID compared by the ID comparator 111 and in the case of the transaction coincident as a result of comparison due to the ID comparator 111, a selecting means 105 executes operation for issuing the transaction to the system bus 300 after improving the priority of the selecting means 113.
申请公布号 JP2000259500(A) 申请公布日期 2000.09.22
申请号 JP19990059874 申请日期 1999.03.08
申请人 NEC IBARAKI LTD 发明人 TAKASHIMA HIROMI
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
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