发明名称 CIRCUIT FOR AUTOMATIC-VERIFICATION-PROGRAMMING NON- VOLATILE MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To reduce current consumption by limiting the maximum value of a cell current and reducing stress given to a circuit. SOLUTION: This circuit comprises a voltage clamping section 100 applying clamp voltage VCLAMP to a selected cell FMC, a first active load section 110 supplying a reference current IREF corresponding to threshold voltage of the selected cell FMC, a second active load section 120 supplying an additional current IADD when the selected cell FMC is programmed, and a logic circuit section 130 separating above mentioned each section from the selected cell FMC when the programming is finished.</p>
申请公布号 JP2000260193(A) 申请公布日期 2000.09.22
申请号 JP19990271680 申请日期 1999.09.27
申请人 HYUNDAI MICROELECTRONICS CO LTD 发明人 CHO SHOKO
分类号 G11C11/41;G11C16/06;G11C16/34;G11C17/00;(IPC1-7):G11C16/06 主分类号 G11C11/41
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