| 摘要 |
PROBLEM TO BE SOLVED: To prevent a scale of a decode circuit from being increased even when a parallel expansion number is increased by devising a header assignment method in the case of transition from a hunting state to a preliminary synchronization state so as to impose a load on a 53-base counter thereby simplifying the circuit. SOLUTION: In the case that a protection circuit 4 discriminates a hunting state H and either of two full expansion CRC arithmetic circuits 2, 3 detects a header in this parallel synchronization circuit, a 53-base counter 5 is loaded. A load value selection circuit 6 loads '1' when the header indicates a 1st parallel value P1 or '27' when the header indicates a 2nd parallel value P2 respectively to the 53-base counter 5. The 53-base counter 5 runs freely. When the header normally takes a 53-byte period, each header is periodically repeated such that a succeeding header is detected as a 2nd parallel value P2 with a count '26' and a header next to the succeeding header is detected as a 1st parallel value P1 with a count '53'. |
