| 摘要 |
PROBLEM TO BE SOLVED: To shorten man-hour for LSI evaluation time and shorten development time taken for LSI development by confirming internal timing outputted from an internal circuit from the outside in an LSI mounted on a device to be a target and quickly detecting debug leakage in logic simulation in verifying an LSI(large scale integrated circuit) design when a device is evaluated. SOLUTION: This debugging circuit has an I/O(input-output) register 3 capable of writing data with which an internal timing signal is selected, a decoder 4 which decodes the data of the register 3 and generates a selection signal selecting the internal timing signal and a selection circuit group 5 which selects the internal timing signal of a logic circuit 2 according to the selection signal and quickly and also surely debugs the operation deficiency of the LSI by directly observing the internal timing signal from an external output terminal group 6 for debugging. |
