| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronizing type semiconductor memory in which chip size can be reduced by decreasing the number of peripheral data lines while adopting a pre-fetch system by which speed of data transfer cycle is increased. SOLUTION: Data of a bit line read out from a memory cell array 2, data of 2 bits per an I/O terminal are transferred in parallel to DQB (E), DQB (O) through pairs of main data line MDQ (E), bMDQ (E), MDQ (O), bMDG (O). The DQB (E) and DQB (O) have a sense amplifier 24 and a latch circuit 25 respectively. A order of taking out 2 bit data is discriminated by the lowest column address, the leading data are passed through the latch circuit 25 in the DQB (E) and transferred to a peripheral data line RD. The while, successive data are temporarily held in the latch circuit 25 in the DQB (O), after that, transferred to the peripheral data line RD being same as the leading data.
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