METHOD FOR ESTIMATING WIRING LENGTH OF LSI AND METHOD FOR ESTIMATING AREA OF LSI

摘要

PROBLEM TO BE SOLVED: To provide a highly accurate layout estimation method even in the estimation of wiring length having a large fan-out number causing the generation of a large error in the case of estimating the wiring length by an estimation method similar to a conventional method because the number of networks belonging to the fan-out number is small and it is difficult to statistically execute the estimation. SOLUTION: The method is provided with a process ST52 for estimating wiring length S [FN] in each fan-out number on the basis of a network list describing the logical cell connection information of an LSI and a cell library for storing the information of logical cells and a process ST02 for correcting the estimated wiring length in each fan-out number on the basis of the product number of the half peripheral length LH of the total area of standard cells constituting the circuit, the fan-out number FN and an adjustment parameterα.