| 摘要 |
PROBLEM TO BE SOLVED: To facilitate an optimization operation of an instruction code operating on a processor. SOLUTION: An instruction memory 110 at least stores an address acquisition instruction 116 which instructs the execution of address acquisition processing in which an address value is outputted to a register. An instruction decoder 120 is provided with an address acquisition instruction interpreting part 121 that discriminates whether or not an instruction code output is the instruction 116, an arithmetic and logical circuit controlling means 122 which makes an arithmetic and logical circuit 130 output an output value of a program counter delayed to desired timing when the instruction code output is the instruction 116, a selector controlling means 123 which makes a selector 112d select and output an output from the circuit 130 and a register controlling means 124 which allows writing to registers 113 and writes an output from the selector 112d in the registers.
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