发明名称 TERNARY LOGIC SYSTEM ARITHMETIC UNIT
摘要 PROBLEM TO BE SOLVED: To realize a complicated logic operation with a simple system constitution in a small scale by inputting a ternary signal where undecidability (NIL) is allocated as a third truth value in addition to true/false binary, executing a prescribed logic operation and outputting the result of the logic operation as the ternary signal. SOLUTION: When two input signals XA1 and XA2 are inputted to a ternary AND gate 1, an output signal YA is outputted. The lower voltage in the signal voltages of the input signals XA1 and XA2 is outputted as the output signal YA. When the signal voltages of the input signals XA1 and XA2 are identical, the voltage is outputted as the output signal YA. That is, at least one of the input signals XA1 and XA2 which are inputted to the AND gate 1 is '0', the output signal YA becomes '0'. When both input signals XA1 and XA2 are '1', the output signal YA becomes '1'. When the input signals XA1 and XA2 are the combination of 'NIL' and '1' or 'NIL' and 'NIL', the output signal YA becomes 'NIL'.
申请公布号 JP2000261309(A) 申请公布日期 2000.09.22
申请号 JP19990062955 申请日期 1999.03.10
申请人 CSK CORP 发明人 NAKAMURA KAZUTO
分类号 H03K19/20;(IPC1-7):H03K19/20 主分类号 H03K19/20
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