发明名称 DIGITAL VIDEO SIGNAL PROCESSING UNIT
摘要 PROBLEM TO BE SOLVED: To easily realize a digital zoom processing circuit that corrects an offset of a time base such as jitter or skew that is produced and adjusts a horizontal display rate in accordance with fluctuation in a horizontal period through a simple circuit configuration. SOLUTION: Reduced interpolation is applied to a digital video signal that is A/D converted and the digital is interleaved and written to a memory 3, and the signal is read from an interpolation processing circuit at a required clock rate. An arithmetic magnification controlled by a horizontal display rate control circuit 8 is given to an interpolation coefficient calculation circuit 6 to calculate an interpolation coefficient and controls a write control circuit 4 to conduct interpolation processing. Furthermore, Horizontal reference position control by the interpolation coefficient calculation circuit 6 is applied to obtain jitter of an integer part of an operating clock and jitter of a fraction part (phase component) is obtained by offsetting an interpolation coefficient of the interpolation coefficient calculation circuit 6 to realize jitter correction and horizontal zoom and horizontal direction display rate control at once by one interpolation circuit.
申请公布号 JP2000261720(A) 申请公布日期 2000.09.22
申请号 JP19990062770 申请日期 1999.03.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUMOTO KEIZO;NOZAKI HIDEKI
分类号 H04N5/91;H04N3/22;H04N5/228;H04N5/262;H04N9/87;(IPC1-7):H04N5/262 主分类号 H04N5/91
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