发明名称 A process line for underfilling a controlled collapse chip connection (c4) integrated circuit package
摘要 A high throughput process line and method for underfilling an integrated circuit that is mounted to a substrate. The process line includes a first dispensing station that dispenses a first underfill material onto the substrate and an oven which moves the substrate while the underfill material flows between the integrated circuit and the substrate. The process line removes flow time (wicking time) as the bottleneck for achieving high throughput.
申请公布号 AU2986100(A) 申请公布日期 2000.09.21
申请号 AU20000029861 申请日期 2000.02.08
申请人 INTEL CORPORATION 发明人 DUANE COOK;SURESH RAMALINGAM
分类号 H01L21/56 主分类号 H01L21/56
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