METHOD FOR PRODUCING A DRAM STRUCTURE WITH BURIED BIT LINES OR TRENCH CAPACITORS

摘要

According to the invention, the substrate comprises a recess (V). The bottom and the sides of the lower part of said recess (V) are provided with an insulating structure (I1). A first part (L1) of the conductive structure of a first type of electric conductivity is located in the lower part of the recess (V). A second part of the conductive structure (L2) of a second type of electric conductivity that is lower than the first electric conductivity is located in a upper part of the recess (V) and borders the region of the substrate (1) at least in a part of the sides of the recess (V). The conductive structure is provided with a diffusion barrier (D) that is arranged between the first part (L1) and the second part (L2) of the conductive structure. In a first embodiment, the conductive structure (L1,D,L2) is configured as a bit line pertaining to a DRAM cell arrangement with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represesents the upper source/drain area connected to a memory capacitor. In a second embodiment, the conductive structure (L1', D', L2') is configured as a memory capacitor and the upper source drain/area is connected to a bit line.