| 摘要 |
To prevent a through current from flowing through a pair of MOS transistors of the final stage forming a push-pull buffer circuit, a reset circuit is provided which receives signals individually from two inverter gate groups of a control system and an output system disposed at the stage preceding the push-pull buffer circuit and which delays the input signals and makes a logical decision on them; even in the case where an input/output circuit formed by two power supply systems becomes unstable at the time of power ON-OFF operation and the signal output from a signal level converter circuit yields logic that causes a through current flows into the final stage, the reset circuit forcedly cancels this logic by feedback. <IMAGE> |
