发明名称 |
Multi-bank memory input/output line selection |
摘要 |
A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second series-connected switches. The first switches are input/output switches that are controlled by column select signals that are shared between multiple banks. The second switches are bank select switches that are controlled by a bank decoder, for coupling only one of the banks to input/output lines and isolating the other banks from input/output lines. The invention reduces timing requirements between operations in different banks, and allows concurrent operations in different banks, thereby increasing the speed at which the memory operates.
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申请公布号 |
US6122217(A) |
申请公布日期 |
2000.09.19 |
申请号 |
US19990244573 |
申请日期 |
1999.02.04 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
KEETH, BRENT;MANNING, TROY A. |
分类号 |
G11C7/10;G11C8/12;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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主权项 |
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地址 |
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