发明名称 |
Integrated circuit planarization and fill biasing design method |
摘要 |
An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.
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申请公布号 |
US6121078(A) |
申请公布日期 |
2000.09.19 |
申请号 |
US19980154652 |
申请日期 |
1998.09.17 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DEBROSSE, JOHN K.;WORDEMAN, MATTHEW R. |
分类号 |
H01L21/762;H01L21/82;H01L27/06;(IPC1-7):H01L21/338 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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