| 摘要 |
A pipelined circuit contains a cascade of stages, each with an intial register followed by a combinatorial logic circuit. The registers are clocked. At the beginning of each clock period, data in the initial register is updated. After that, during the clock period, data propagates from the initial register, along a path through the combinatorial logic circuits, to the initial register in the next stage where it is stored at the beginning of the next cycle. In the path there are several other registers, in which the data is stored at intermdiate phases of the clock cycle, while the data is kept in the initial register. Thus differences in propagation delay along different branches of the path are eliminated without increasing the number of clock cycles needed to pass data through the pipelined circuit. This reduces the number glitches which consume energy without affecting the function of the circuit.
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