| 摘要 |
PCT No. PCT/KR97/00018 Sec. 371 Date Feb. 9, 1999 Sec. 102(e) Date Feb. 9, 1999 PCT Filed Jan. 30, 1997 PCT Pub. No. WO97/28604 PCT Pub. Date Aug. 7, 1997Disclosed is an energy economized pass-transistor logic having a level restoration circuit (50) free from leakage and a full adder using the same. The logic comprises a functional block (10) having a plurality of n type FETs (M1 . . . M4), for performing at least one logical function of inputs (12, 14, 16, 18) to generate two complementary signals (20, 22), the complementary signals (20, 22) being a weak high level signal and a strong low level signal; and a level restoration block (50) having first and second CMOS inverters (52, 54), for restoring the weak high level signal to a strong or full high level signal and preventing a leakage current flowing through one of the first and the second CMOS inverters (52, 54) where the weak high level is applied.
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