Variable time delay circuit and method

摘要

A high resolution variable time delay circuit is disclosed. In one embodiment, a current digital to analog converter (DAC) is used to sequentially charge two capacitors having similar capacitance construction. A threshold level capacitor provides the threshold level to a comparator, and a ramping capacitor is used for ramping to the threshold to provide a delay time. The comparator provides a delayed pulse using the threshold level provided by the threshold level capacitor and the ramp provided by the ramping capacitor. Thus, resolution is better than that provided by digital elements alone. This circuit also automatically cancels errors due to capacitance variations and unit current variation of the DAC introduced during the manufacturing process. In another embodiment a single capacitor is used in combination with two current DACs and a comparator to provide a controllable time delay.