发明名称 |
Cache coherency controller of cache memory for maintaining data anti-dependence when threads are executed in parallel |
摘要 |
Disclosed is a cache coherency controller used in a multi-processor system. The cache coherency controller reflects a cache line including data produced by a preceding thread to a cache line including data produced by a succeeding thread. On the other hand, the cache coherency controller prevents a cache line including data produced by the succeeding thread from being reflected to the cache line including data produced by the preceding thread. The cache coherency controller maintains a sequential order (relationship) among threads based on a thread sequence information table and thereby maintains data anti-dependence.
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申请公布号 |
US6122712(A) |
申请公布日期 |
2000.09.19 |
申请号 |
US19970946061 |
申请日期 |
1997.10.07 |
申请人 |
NEC CORPORATION |
发明人 |
TORII, SUNAO |
分类号 |
G06F9/38;G06F9/46;G06F9/52;G06F12/08;G06F15/16;G06F15/177;(IPC1-7):G06F12/12;G06F12/16 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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