发明名称 |
On-chip bus architecture that is both processor independent and scalable |
摘要 |
A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus interface for either a bus master functional block or a slave functional block. Each bus interface includes a state machine that has at least two operational modes including a fast operational mode having two states and a normal operational mode having at least four states. A bus interface coupled to a bus master functional block implements an operational mode and a bus interface coupled to a slave functional block operates in a complementary operational mode. Each bus interface is also equipped to facilitate scaling of the address and/or data width on the bus. Various embodiments of the bus interfaces are also equipped to support multiple bus masters, broadcast writes, burst mode transfers, and/or tri-states on the bus.
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申请公布号 |
US6122690(A) |
申请公布日期 |
2000.09.19 |
申请号 |
US19980062363 |
申请日期 |
1998.04.17 |
申请人 |
MENTOR GRAPHICS CORPORATION |
发明人 |
NANNETTI, GIANNI MICHELE;PARVATANENI, TIRUMAL RAO |
分类号 |
G06F13/42;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/42 |
代理机构 |
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主权项 |
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地址 |
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