| 摘要 |
A pipeline structure processes data in a series of stages, each of which has a data input latch (LDIN) and passes it on to the next stage in the pipeline via a data output latch (LDOUT). The stages are preferably connected to two non-overlapping clock phases (PH0, PH1) Adjacent stages are also connected via a validation line (IN-VALID, OUT-VALID) and an acceptance line (IN-ACCEPT, OUT-ACCEPT), and in some embodiments also via an extension bit line (IN-EXTN, OUT-EXTN). Input data is transferred from any stage to the following device on every complete period of both clock signals only if both the validation and acceptance signals in the respective latch are in an affirmative state, whereby data is transferred between stages regardless of the state of the validation and acceptance signals in other stages. A two-wire interface is thus formed between the stages. Address decoding circuitry may also be included in any of the stages so that a stage manipulates the input data stream only when one or more current data words have a predetermined bit pattern. The extension bit line conveys an extension bit that separates fields of different data blocks in the data stream. The invention also includes a method for uniquely encoding data blocks so that only intended pipeline stages are activated, with others simply passing input data through.
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