| 摘要 |
Comparator structures are shown which improve latching accuracy and enhance bandwidth for operations such as high-speed sampling in a variety of applications (e.g., analog-to-digital converters and automatic test equipment). The structures include an input differential pair of transistors having first and second control structures, a differential output amplifier and a clamp that limits the signal level of at least one of the first and second control structures. The clamp includes first and second Schottky diodes that are oppositely oriented and coupled between the first and second control structures. Altenatively one side of the diodes can be coupled to bias structures that respond to a threshold signal. Bias networks respond to a sampling threshold signal and stabilize biases in the input differential pair and the differential output amplifier. A differential input buffer preferably precedes the input differential pair and a diode bridge is positioned between these elements to limit current from the differential input buffer. To facilitate sampling, a latch maintains a current state of the differential output amplifier.
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