| 摘要 |
A process for forming implanted regions at an optimal location in a semiconductor substrate underneath a patterned polysilicon gate of an MOS transistor. The process includes steps of first providing a semiconductor substrate (e.g. a silicon wafer) with a gate oxide layer on its surface, followed by the formation of a polysilicon gate layer on the gate oxide layer. An additional oxide layer is subsequently formed on the polysilicon gate layer. The resulting structure is then patterned to form a patterned additional oxide layer and a patterned polysilicon gate layer, all of which are subsequently covered by a conformal silicon nitride layer. Next, the conformal silicon nitride layer is anisotropically etched to form spacers on the sidewalls of the patterned structure. After removal of the patterned additional oxide layer, leaving the spacers projecting above the patterned polysilicon gate layer, dopant atoms are implanted through the patterned polysilicon gate layer and into the semiconductor substrate using the spacers as an implant mask. By the proper selection of spacer dimensions, implant energy and implant angle, the portion of the implanted region with the highest dopant atom concentration can be placed at the optimum location (e.g. the lateral edges of LDD extension regions in a channel region and the interface between the gate oxide layer and the channel region). The implanted region then serves as a halo implant region to suppress the drain-induced barrier lowering effect without extensive counterdoping of the LDD extension regions or the creation of parasitic junction capacitance.
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