发明名称
摘要 A direct conversion receiver includes a reference clock signal generating section for generating reference clock signal. An amplifier section amplifies a received signal and extracts a desired signal from the amplified signal. An extraction reference clock signal generating section frequency-divides the reference clock signal based on a frequency division data to generate first and second extraction reference clock signals. An extracting section extracts a data from the desired signal and the first and second extraction reference clock signals. A control and processing section outputs the frequency division data to the extraction reference clock signal generating section and processes the data based on a control section clock signal corresponding to the reference clock signal.
申请公布号 JP3088368(B2) 申请公布日期 2000.09.18
申请号 JP19970339550 申请日期 1997.12.10
申请人 发明人
分类号 H04L27/38;H03D7/16;H04B1/16;H04B1/26;H04B1/30;H04B15/00;H04L27/00;H04L27/14;H04L27/227 主分类号 H04L27/38
代理机构 代理人
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