发明名称
摘要 <p>PURPOSE:To cut the propagation error of encoding data at a reception side by generating address information corresponding to the leading position of other data at every sync block, and attaching the address information on a corresponding sync block. CONSTITUTION:A block forming circuit 3 converts a digital image signal into data of block structure, and an encoder circuit 5 divides the encoding data into significant word data representing the characteristic of the block and the other data. A circuit 6 forms the sync block by re-arranging the encoding data so as to arrange the other data between the significant word data, and the circuit 6 generates the address information corresponding to the leading position of the other data at every sync block, and attaches the address information on a corresponding sync block. Thereby, it is possible to prevent a propagation error continued until one frame period is completed even when an error exists in a dynamic range DR.</p>
申请公布号 JP3089475(B2) 申请公布日期 2000.09.18
申请号 JP19890158903 申请日期 1989.06.21
申请人 发明人
分类号 H04N5/92;G11B20/12;H04N7/24;H04N19/00;H04N19/115;H04N19/15;H04N19/176;H04N19/196;H04N19/423;H04N19/46;H04N19/587;H04N19/625;H04N19/65;H04N19/70;H04N19/85;H04N19/91;H04N19/98 主分类号 H04N5/92
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