| 摘要 |
PURPOSE: A data load clock generator for a PDP(plasma display panel) TV is provided to effectively load R, G and B data by effectively controlling data transfer from a triple video ADC(Analog to Digital Converter) to a multiplexer. CONSTITUTION: A data selection logic unit(110) controls a multiplexer and provides R, G and B data transferred from a triple video ADC to the multiplexer to a top data processor and a bottom data processor. The data selection logic unit(110) comprises an AND gate(110a) that performing AND for the effective data about the R, G and B data and a reference clock, a binary counter(110b) that counts digital signal of the output waveform of the AND gate(110a) corresponding to 0 and 1, and a decoder(110c) that decodes an even load and an odd load from the output waveform of the binary counter(110b).
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