| 摘要 |
PURPOSE: A speed detecting system is provided to detect a revolution speed with a high accuracy by adding an algorithm capable of correcting a variation in data for detecting a speed. CONSTITUTION: A speed detecting system comprises an encoder pulse counter(11), a clock counter(14), an operation part(20) and a memory(21). The encoder pulse counter(11) counts the number of pulses generated by an encoder and stores an encoder pulse counted value on the basis of a predetermine signal. The clock counter(14) has a clock pulse counter(15), an interrupt buffer(16) storing a predetermined interrupt generation cycle, a first buffer(18) storing a clock count value of the clock pulse counter, and a second buffer(19) storing the clock count value of the first buffer. The clock counter(14) generates a speed detection interrupt to the operation part at a predetermined cycle. Upon generation of the speed detection interrupt, the operation part executes the interrupt for calculating a speed on the basis of the interrupt generation cycle, an encoder pulse count value stored in the encoder pulse counter and a value stored in the first buffer, and calculates the speed using a clock count value stored in the second buffer instead of the clock count value stored in the first buffer when a new encoder pulse is generated by the encoder during an execution time starting from the point of time of generation of the speed detection interrupt to a point of time of actual execution of the interruption. |
