发明名称 |
PHASE SPLITTER |
摘要 |
PURPOSE: An identical delay and converted phase buffer is provided to reduce the number of a compositing device when panning out is increased. CONSTITUTION: The buffer includes a delay and conversion delay portions(10), pull up and pull down portions(20) and an outputting portion(30). The delay and conversion delay portions output a conversion delay output signal converted and delayed an input signal and a non-conversion delay output signal delayed the input signal so as to have a state a high voltage and a ground voltage whose voltage value is larger than a power voltage. The pull up and pull down portions receive the conversion delay output signal and the non-conversion delay output signal of the delay and conversion delay portion and output an output signal, which is the same a phase as the input signal and is delayed during a predetermined time, having a state of a low voltage whose voltage value is lower than that of the high voltage and the ground voltage. The outputting portion outputs an output signal having a state of a power voltage and a ground voltage by converting and delaying an output signal of the pull up and pull down portion and an output signal having a state of the power voltage and the ground voltage by delaying the output signal of the pull up and pull down portion.
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申请公布号 |
KR100266642(B1) |
申请公布日期 |
2000.09.15 |
申请号 |
KR19970066972 |
申请日期 |
1997.12.09 |
申请人 |
HYUNDAI MICRO ELECTRONICS CO., LTD. |
发明人 |
LEE, JAE-GOO;KIM, HA-SOO;KIM, TAE-HYOUNG |
分类号 |
G11C7/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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