发明名称 CIRCUIT FOR MULTI-INPUT/-OUTPUT STRUCTURE MEMORY
摘要 PURPOSE: A memory circuit having a multi input and output structure is provided to perform a stable operation although a bit number of input and output is increased. CONSTITUTION: The memory circuit includes first and second enable controlling portions(600,500), first and second bank portions(100,200), a bus, first and second input/output limiting portions(700,800) and first and second input/output portions(300,400). The first enable controlling portion receives an address signal(ZADDR) and generates enabling signals(AZNB,AZN). The second enable controlling portion receives an address signal(YADDR) and generates enabling signals(YSAB,YSA). The first bank portion outputs an output data of 8 bits or 16 bits stored according to the enabling signals(AZNB,YSAB,YSA) or receives and stores an output data of 8 bits or 16 bits from the outside. The second bank portion outputs an output data of 8 bits or 16 bits stored according to the enabling signals(AZN,YSAB,YSA) or receives and stores an output data of 8 bits or 16 bits from the outside. The bus is separated into a large number of buses, which are respectively independent, according to a state of fuses(FUSE1-FUSE3). The first input/output limiting portion receives an output enabling signal and the enabling signals(AZNB,AZN) and outputs an input/output controlling signal. The second input/output limiting portion receives a write enabling signal and the enabling signals(AZNB,AZN) and outputs the input/output controlling signal. The first input/output portion outputs an output data of the first bank portion recorded to the bus to the outside according to an input/output controlling signal of the first and second enable controlling portions, or stores a data out of the outside to the first bank portion through the bus. The second input/output portion outputs an output data of the second bank portion recorded to the bus to the outside according to the input/output controlling signal of the first and second enable controlling portions, or stores a data out of the outside to the second bank portion through the bus.
申请公布号 KR100266663(B1) 申请公布日期 2000.09.15
申请号 KR19980002671 申请日期 1998.01.31
申请人 HYUNDAI MICRO ELECTRONICS CO., LTD. 发明人 LEE, JUNG-YONG;NA, JOON-HO
分类号 G11C7/00;G11C7/10;(IPC1-7):G11C7/00 主分类号 G11C7/00
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