发明名称 REFERENCE CLOCK DISTRIBUTOR UNIT INSIDE BASE STATION OF WIRELESS LOCAL LOOP SYSTEM
摘要 PURPOSE: A reference clock distributor unit(RDU/CDU) inside a base station of a wireless local loop(WLL) system, is provided to distribute every kind of analog and digital reference clock needed to every configured clock inside the base station by using only sine wave oscillator of 10MHz, and to integrate RDU related to digital clocks and CDU related to analog clocks into one. CONSTITUTION: A reference clock distributor unit(RDU/CDU) inside a base station of a wireless local loop(WLL) system, comprises the circuits as follows. A reference clock selector(11) selects a most excellent clock among network synchronizing clocks(reference clocks of 2.048MHz and 8KHz, 4KHz duplexing clocks) inputted from externals(E1RPC/other RDUs) and clocks of 16.384MHz generated from an external oscillator. A frequency/phase detector(12) outputs information to generate synchronizing clocks, by inputting the 4KHz and 16.384MHz clocks and detecting frequencies/phases of reference clocks to make clocks synchronized with an upper system(base station controller) generated. A clock monitoring circuit(13) monitors an operation of the frequency and phase detector(12). A CPU(14) outputs a control signal according to information for generating a synchronizing signal output from the frequency/phase detector(12). A digital-to-analog(D/A) converter(15) converts the control signal in digital into an analog signal. A 10MHz sine wave oscillator(16) generates 10MHz sine wave according to the converted control signal. An analog clock distributor(17) outputs 22-port 7dB 10MHz sine wave clocks in analog to a down converter card(DCC), an up converter card(UCC) and an analog common & sector interface unit(ACSU) inside an RF device, by distributing the 10MHz sine wave with different rates through a driving chip. A transistor-transistor logic(TTL) converter(18) inputs one clock among 22-port 7dB 10MHz sine wave clocks, for TTL-converting. A 32.768MHz amplifier(19) generates clocks of 32.768MHz by amplifying the TTL-converted sine wave clocks. And a digital clock distributor(20) outputs every kind of digital clock, by frequency-demultiplying the 32.768MHz clocks with different rates through every kind of frequency demultiplier to supply to channel cards and the E1RPC.
申请公布号 KR20000055946(A) 申请公布日期 2000.09.15
申请号 KR19990004865 申请日期 1999.02.11
申请人 HYUNDAI ELECTRONICS IND. CO., LTD. 发明人 CHEON, HYEONG JUN
分类号 H04B7/155;(IPC1-7):H04B7/155 主分类号 H04B7/155
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