| 摘要 |
PURPOSE: A circuit for controlling an input and output data of an FIFO memory is provided to prevent an error and a data loss according to the increasement of a read position signal and a write position signal. CONSTITUTION: The circuit includes first and second D-flip flops(D-FF11,D-FF12), the first exclusive OR gate(XOR11), first through third AND gates(AND11-AND13), and the first OR gate(OR11). In the first and second D-flip flops, a write position controlling portion respectively receives a clear signal(CLR) to a clear terminal through the first inverter and a write controlling signal(WC) to a clock terminal through the second inverter and outputs a write position signal(WPOS) through each output terminal. The first exclusive OR gate receives a full signal(FULL) of a FIFO memory to one side and an output of the first D-flip flop inversion output terminal to other side, mixes using an exclusive OR operation and outputs to an input terminal of the first D-flip flop. The first AND gate receives an output of an inversion output terminal of the first D-flip flop and an output terminal of the second D-flip flop and mixes using an AND operation. The second AND gate receives the full signal of the FIFO memory and the output of the output terminal of the second D-flip flop and mixes using the AND operation. The third AND gate receives the full signal of the FIFO memory through the third inverter and the output of the output terminal of the first D-flip flop and the inversion output terminal of the second D-flip flop and mixes using the AND operation. The first OR gate receives an output of the first through third AND gates, mixes using the OR operation and outputs to the input terminal of the second D-flip flop. The read position controlling portion is composed so as to output a read position signal from the output terminal of the first and second D-flip flop by inputting an empty signal of the FIFO memory to one side of the exclusive OR gate and simultaneously a read controlling signal to an input terminal of the second inverter in the write position controlling portion.
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