| 摘要 |
PROBLEM TO BE SOLVED: To output data without causing any phase deviation in an external clock at the time of generating an internal clock synchronously with the external clock and controlling the data output operation at an off-chip driver circuit by using the internal clock. SOLUTION: This circuit has an off-chip driver circuit, a synchronous circuit 31, which outputs an internal clock Tu that is synchronized to an external clock CK, a synchronous circuit 32, which outputs an internal clock Td having a phase that is 180 deg. shifted with respect to the clock CK, a synchronous circuit 33, which outputs an internal clock aTx1 that is synchronized to the clock Tu and has a phase that is advanced at least for the amount equivalent to a signal delay time in the off-chip driver circuit, a synchronous circuit 34, which outputs an internal clock aTx2 that is synchronized with the clock Td and has a phase that is advanced at least for the amount equivalent to a signal delay time in the off-chip driver circuit, and an OR circuit 35 into which clock aTx1 and aTx2 are inputted. |
