发明名称 DATA TRANSMISSION AND RECEPTION SYSTEM
摘要 PROBLEM TO BE SOLVED: To obtain a system which is hardly affected by clock jitters by allowing a data transmitting node to generate internal data clock information, to receive data clock information from a data receiving node to select one between the internal data clock information and the data clock information and to transmit data by synchronizing it with the selected clock information. SOLUTION: A data receiving node 102 receives a data packet, and an unpacketing means 306 fetches a time stamp and audio data. A comparing means 307 and a PLL 308 reproduce an audio clock on the basis of the fetched time stamp. A selecting means 309 selects either an audio clock generated by an audio clock generating means 303 or the audio clock reproduced by the PLL 308. In this data transmission and reception system, a data receiving node 310 makes audio data synchronize with the audio clock selected by the means 309 and converts it into an analog signal.
申请公布号 JP2000253029(A) 申请公布日期 2000.09.14
申请号 JP19990052352 申请日期 1999.03.01
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MURAKI KENJI;NAKAJIMA KOJI;EJIMA NAOKI;KONDO TOSHIYUKI
分类号 H04L7/033;H04L7/04;H04L12/40 主分类号 H04L7/033
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