| 摘要 |
PROBLEM TO BE SOLVED: To activate a word line in a hierarchical form by equalizing the number of timing-critical address lines to the number of banks, and connecting plural exclusive address lines to respective one of each block. SOLUTION: After a first bank is decoded using a timing signal of a signal line 300, a timing signal of the signal line 300 is transferred, a single memory block 330 is decoded in the bank, lastly, a single word line WL is activated, and the third decoding is performed by a shared row decoder/word line driver 61. At the beginning, a pre-decoded address signal of the signal line 300 including timing information is used at a first level of hierarchical decoding, after a single bank of a unit is activated, an address signal in the signal line 300 is multiplexed with other addresses pre-recorded statically in a signal line 310 having possibility for continuous variation independently of a bank address.
|
