发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, WIRING LAYOUT GENERATING METHOD, AND RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To reduce the generation of coupling noise while actulizing high integration by providing change parts for changing the arrangement order of signal wires at halfway or branch points of the signal wires so that the parallel wire length of the signal wires is less than a prescribed value. SOLUTION: A bus line BL1 is provided with 1st to (S)th change parts Ha1 to Has (S: natural number based upon the value of (n)) halfway. The arrangement order of signal lines D1 to Dn of a 1st segment W1 is changed by the 1st change part Ha1 in a 2nd segment W2 in the order of D2, D4, D6... D(n-5), D(n-3), and D(n-1). The arrangement order of the signal lines D1 to Dn in the 2nd segment W2 is changed by the 2nd change part Ha2 in a 3rd segment W3 in the order of D4, D8, D12... D(n-11), D(n-7), and D(n-3). The arrangement order of the signal lines D1 to Dn in an (S)th segment WS is changed by the (S)th change part Has in an (s+1)th segment W(S+1) in the order of D(n/2+1), D1, D(n/2+2), D2...D(n-1), D(n/2-1), Dn, and D(n/2).
申请公布号 JP2000250961(A) 申请公布日期 2000.09.14
申请号 JP19990054047 申请日期 1999.03.02
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 KOMAKI MASAKI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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