发明名称 SEMICONDUCTOR INTEGRATED-CIRCUIT DEVICE AND INSPECTION METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To reduce an area occupied by an inspection circuit which is used to inspect a memory circuit and to shorten the inspection time. SOLUTION: In an LSI 1 as this device, pieces of circuit information as pieces of inspection program information which are used to change a field programmable gate array(FPGA) 2 into an inspection circuit used to inspect a memory device are written in a first memory device 10a to a third memory device 10c. Then, an FPGA control circuit 3 by which, when an inspection is executed, the pieces of inspection program information in the first to third memory devices 10a to 10c are written sequentially in the FPGA 2, by which the FPGA 2 is operated as an inspection circuit, and by which the first to third memory devices 10a, to 10c are controlled so as to be inspected sequentially, is installed.
申请公布号 JP2000252361(A) 申请公布日期 2000.09.14
申请号 JP19990049236 申请日期 1999.02.26
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OKUNO KUNITAKA;SEGAWA OSAMU;MIZOKAWA TAKU
分类号 G06F11/22;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F11/22
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