| 摘要 |
PROBLEM TO BE SOLVED: To simply and accurately obtain a delay to be applied to a clock signal. SOLUTION: A control section 5 in this phase adjustment device sets a frequency division ratio, at which a clock signal generating section 1 applies frequency division to a horizontal synchronizing signal to a value different from a predetermined reference value. The clock signal generating section 1 applies frequency division to the horizontal synchronizing signal at the frequency division ratio set by the control section 5, to generate a clock signal and to give it to a sampling section 3. The sampling section 3 samples an externally received analog video signal with a timing specified by the clock signal. A sampling mistake detection section 4 detects a sampling errors at each sampling point and informs the control section 5 about it. The control section 5 specifies a sampling point, at which largest number of sampling errors takes plate, obtains a delay to cause most sampling errors at a predetermined reference point and informs a signal delay section 2 about the delay. The signal delay section 2 adjusts a delay applied to the clock signal according to the delay information received from the control section 5. |
